VLSI CAD Lab

Very Large Scale Integration Computer Aided Design Laboratory

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TDS Papers
Papers related to TDS, TEDify and TED
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# Article Title Author Hits
1 Taylor Expansion Diagrams: A Canonical Representation forHigh Level Design Verification Administrator 553
2 Taylor Expansion Diagrams: A Compact, Canonical Representation with Applications to Symbolic Verification Administrator 1526
3 Data-Flow Transformations using Taylor Expansion Diagrams Administrator 1445
4 Taylor Expansion Diagrams: A Canonical Representation for Verification of Data Flow Designs Administrator 1237
5 Efficient Factorization of DSP Transforms using Taylor Expansion Diagrams Administrator 1153
6 Variable Ordering for Taylor Expansions Diagrams Administrator 824
 

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